Undergraduate Thesis - Project — A basic Microkernel for the RISC-V Instruction set architecture The following is my Undergraduate thesis (incomplete). There are many errors and issues I am aware of. The idea is to implement a Microkernel for the RISC-V Instruction Set Architeture for... Read more—
Hi, I'm Ben Mezger, a Researcher and Backend developer.
Interrested in computer security and computer architecture -- about me
Vim Cheatsheet — This is still an ongoing post, so some things may be incomplete. Using Vim buffers Closing buffers Unload buffer [N] (default: current buffer) and delete it from the buffer list. If the buffer was changed, this fails, unless when [!]... Read more—
RISC-V notes — Operands Fast location for data. All data must be in registers to perform arithmetic. Register x0 always equals to 0.. Register x0 always equals to 0. 32bit registers x0-x31 RISC-V uses bytes addresses; sequencial doubleword accesses differ by 8. Memory... Read more—
Note to self – Reverting Git — One thing that bothers me is that I always forget how to revert commits properly. So I decided to finally write a quick "cheatsheet" on how to revert commits on various cases. Undo a whole commit by creating a new... Read more—