March 1, 2021
tags RISCV Compiler After an hour of compiling RISC-V’s toolchain, I ran riscv64-unknown-elf-gdb remotely against my Rust kernel running in Qemu. This happened.
riscv64-unknown-elf-gdb \ -q \ -ex 'file target/riscv64gc-unknown-none-elf/debug/strail-rs' \ -ex 'target remote localhost:3333' \ -ex "b main" Reading symbols from target/riscv64gc-unknown-none-elf/debug/strail-rs... I'm sorry, Dave, I can't do that. Symbol format `elf64-littleriscv' unknown. Remote debugging using localhost:3333 make: *** [gdb] Abort trap: 6 What the hell. I immediately started to investigate what is going on, is it my build system?
November 16, 2020
tags RISCV Computer Architecture Notes on RISC-V CPU HARD IP Cores enter SoC FPGAs presentation
Frozen base ISA Consolidation in the semiconductor industry RISC-V is not owned by anyone Custom instruction extension to extend the virtuous cycle of semiconductor innovation PolarFire SoC - RISC-V enabled innocation platform # Mixed critically RTOS + Linux support Defence grade security Exceptional reliability Designed for low-power L2 memory subsystem Can be made to be deterministic Not all L2 are deterministic
May 31, 2020
tags Computer Science Operating Systems Computer Architecture Understanding RISCV stack pointer # L06 RISCV Functions(6up).pdf # Exceptions # Exception are unusual condition occurring at run time associated with an instruction in the current RISCV thread. Exceptions may be converted to traps, but that all depends on the execution environment.
Traps # Trap refers to the synchronous transfer control to a trap handler caused by an exceptional condition occurring within a RISC thread.